1. Field of Invention
The present invention relates to a method for manufacturing mixed-mode devices. More particularly, the present invention relates to a method for eliminating watermarks in the neighborhood of shallow trench isolation (STI) during the process of fabricating a dual-gate oxide layer.
2. Description of Related Art
FIG. 1 is a cross-sectional view showing a shallow trench isolation structure according to a conventional method. Shallow trench isolation is now common in integrated circuit fabrication because a conventional LOCOS isolation method is incapable of achieving isolation for feature size smaller than 0.3 .mu.m. However, as shown in FIG. 1, a conventional method of fabricating shallow trench isolation generates an inverted trapezium-shaped structure at the upper end of the shallow trench 16. Hence, in carrying out the fabrication of a dual gate-oxide layer, residual material can easily be trapped inside the dead corner space 18 of the inverted trapezium-shaped structure, thereby causing the watermarks to appear.
Products that utilize a dual gate-oxide layer include DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). The technique of forming the dual gate-oxide layer is to allow the application of different operating voltages different devices. In fact, design rules fix the applied current and operating voltage permitted for a gate oxide layer having certain thicknesses. For example, for gate length of 0.25 .mu.m, 0.34 .mu.m and 0.5 .mu.m, their current and operating voltages are 50A/2.5V (0.25 .mu.m), 70A/3.3V (0.34 .mu.m) and 130A/5V (0.5 .mu.m).
When mixed-mode devices are needed on a wafer, the first step is to form a dual gate-oxide layer above a semiconductor substrate. For a substrate having shallow trench isolation structure, the first step for forming a dual gate-oxide layer is to deposit a gate oxide layer over the substrate. Thereafter, a thick gate oxide layer region is defined and covered by a photoresist layer, and then a wet etching method is used to remove the gate oxide layer in the thin gate oxide layer region. Next, another gate oxide layer is formed over the substrate. Hence, a thick gate oxide layer region and a thin gate oxide layer region are created simultaneously on each side of a shallow trench isolation structure. In the subsequent step, conventional production techniques are used to form transistors above the thick gate oxide layer region and the thin gate oxide layer region.
FIGS. 2A through 2E are cross-sectional views showing the progression of manufacturing steps in producing mixed-mode devices according to a conventional method. First, as shown in FIG. 2A, a substrate 10 having shallow trench isolation structure 16 formed thereon is provided. The shallow trench isolation structure 16 has an inverted trapezium-shaped protrusion at the upper end, whose top surface is even slightly higher than the top substrate surface. Therefore, a dead corner space 18 is created at the interface between the slide of trench 16 and the substrate 10. Next, a gate oxide layer 12 is formed over the substrate 10 and the trench 16, and then a photoresist layer 14 is formed over the gate oxide layer 12. Thereafter, photolithographic and etching processes are carried out to pattern the photoresist layer 14 so that it covers the region intended to be the thick gate oxide layer.
Next, as shown in FIG. 2B, the exposed gate oxide layer 12 is removed, and then followed by the removal of the photoresist layer. The process of removing the exposed gate oxide layer 12 includes immersing the wafer in a buffered oxide etchant (BOE) to perform a wet etching operation. Consequently, a residual gate oxide layer 12a underneath the photoresist layer 14 remains in the thick gate oxide layer region. Since the gate oxide layer 12a is still covered by the photoresist layer 14, isopropyl alcohol (EPA) cannot be used to dry the wafer. Instead, a spin drying method is used to remove residual etchant solution. Next, the photoresist layer 14 is removed, and then a cleaning operation using solution such as an RCA cleaning solution is used to rinse the wafer surface. However, during the etching process with buffered oxide etchant, a residual photoresist contaminant 28 may be suspended in the etchant solution. Some of this photoresist contaminants 28 may stick to the dead corner space 18, which makes it very difficult to dislodge by spinning. After a subsequent drying operation, these contaminants 28 around the dead corner space 18 and on the substrate surface are even more difficult to remove, and lead to watermarks. Watermarks not only lead to the contamination of diffusion furnace; they also result in the formation of a non-uniform oxide layer, and hence lowering the product yield rate.
Next, as shown in FIG. 2C, a gate oxide layer 22 is formed over the gate oxide layer 12a and the substrate 10, and then the wafer is washed again. This completes the process for forming a dual gate-oxide layer over the substrate 10. The thick gate oxide layer region 32 includes the gate oxide layer 12a and the gate oxide layer 22, while the thin gate oxide layer region includes just the gate oxide layer 22. However, because the contaminants residing in the dead corner space 18 and on the surface of the substrate diffuse out during the fabrication of the gate oxide layer 22, the gate oxide layer 22 is highly non-uniform.
After the aforementioned processes, two different device regions are established, each region having its own operating voltage. The two different device regions are the thick gate oxide layer device region 29 composed of the gate oxide layer 12a and the gate oxide layer 22, and the thin gate oxide device region 19 composed of just one gate oxide layer 22.
Next, as shown in FIG. 2D, subsequent processes for forming a metal oxide semiconductor (MOS) transistor are carried out. First, a heavily doped polysilicon layer 13 is formed over the thick gate oxide layer device region 29 and the thin gate oxide layer device region 19. The heavily doped polysilicon layer 13, preferably having a thickness of about 2000 .ANG. to 3000 .ANG., can be formed, for example, by a low pressure chemical vapor deposition (LPCVD) process. This is followed by a heat diffusion or an ion implantation process to implant dopants into the polysilicon layer.
Next, as shown in FIG. 2E, the polysilicon layer 13 is patterned to form a gate 13a above the thick gate oxide layer device region 29 and a gate 13b above the thin gate oxide layer device region 19. Thereafter, using the gates 13a and 13b as a mask, an ion-doping operation is carried out to form source/drain regions 17 in the substrate 10 on each side of the gates 13a and 13b. Hence, transistors having different operating voltages are formed above the thick gate oxide layer device region 29 and the thin gate oxide layer device region 19, respectively.
Because the conventional LOCOS isolation method is incapable of achieving isolation for a feature size smaller than 0.3 .mu.m, shallow trench isolation has to be used to isolate the devices. However, the conventional process of forming dual gate-oxide layer creates watermarks over the substrate in the neighborhood of shallow trench isolation structures.
In light of the foregoing, there is a need to provide a method for reducing or eliminating watermarks from the substrate before the fabrication of a dual gate-oxide layer.